(1) Field of the Invention
The present invention relates to a capacitive element having a three-dimensional structure using a ferroelectric material as a capacitor insulating film and a semiconductor memory device using the same.
(2) Description of Related Art
In recent years, ferroelectric films with spontaneous polarization characteristics have been actively researched and developed for the sake of putting into practical use Nonvolatile Random Access Memories (RAM) capable of lower-voltage and higher-speed writing and reading operations than known ones. In particular, in order to realize megabit-class semiconductor memory devices mounted on Large-Scale Integrated Circuits (LSI) composed of Complementary Metal-Oxide Semiconductor (CMOS) transistors each having a design rule of 0.18 μm or less, capacitive elements need be developed which each have a three-dimensional structure to realize a large capacitance in spite of a small area. Such capacitive elements each having a three-dimensional structure usually require the formation of ferroelectric films serving as capacitor insulating films on lower electrodes formed to have uneven surfaces.
In order to achieve higher integration, while capacitive elements need be formed three-dimensionally to reduce their sizes in lateral directions, ferroelectric films need become as thin as possible to secure the capacitances of the capacitive elements. Accordingly, excellent polarization characteristics must be achieved for thin ferroelectric films.
Capacitive elements of a known example will be described hereinafter with reference to FIGS. 6 and 7 (see, for example, Japanese Laid-Open Patent Publication No. 2001-53250).
FIG. 6 shows a cross-sectional structure of an essential part of a known semiconductor memory device (DRAM) having capacitive elements of three-dimensional structures. As shown in FIG. 6, a first silicon oxide film 102 is formed on a semiconductor substrate 101 formed with semiconductor elements and interconnects (not shown) and is formed with n-type impurity-doped plugs 103 of low-resistance polysilicon. A silicon nitride film 104 and a second silicon oxide film 105 are successively deposited on the first silicon oxide film 102 and formed with deep holes 106 to expose the corresponding plugs 103.
Each deep hole 106 has a diameter of approximately 0.3 μm, a depth of approximately 1.3 μm and an aspect ratio of 4 or more. Lower electrodes 107 of polysilicon are formed on the bottom surfaces and inner walls of the corresponding deep holes 106 to roughen their surfaces. A capacitor insulating film 108, which is a layered film of a silicon nitride film and a tantalum pentoxide (Ta2O5) in bottom-to-top order, is deposited to cover the surfaces of the lower electrodes 107. An upper electrode 109 of titanium nitride (TiN) is deposited and formed on the capacitor insulating film 108. A capacitive element for storing information is composed of each lower electrode 107, the capacitor insulating film 108 and the upper electrode 109.
The above publication discloses that, as shown in FIG. 7, a tantalum pentoxide (Ta2O5) film of a high-dielectric-constant material used for the capacitor insulating film 108 is desirably set to have a thickness of 4 through 7 nm to satisfy the following two restrictions: the leakage current should become minimum; and the effective thickness of the tantalum pentoxide film should become minimum in terms of the thickness of a silicon dioxide (SiO2) film.